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| CMOS DUAL SyncFIFOTM DUAL 256 x 18, DUAL 512 x 18, DUAL 1024 x 18 Integrated Device Technology, Inc. IDT72805LB IDT72815LB IDT72825LB FEATURES: * The 72805 is equivalent to two 72205LB 256 x 18 FIFOs * The 72815 is equivalent to two 72215LB 512 x 18 FIFOs * The 72825 is equivalent to two 72225LB 1024 x 18 FIFOs * Offers optimal combination of large capacity (2K), high speed, design flexibility, and small footprint * Ideal for the following applications: - Network switching - Two level prioritization of parallel data - Bidirectional data transfer - Busmatching between 18-bit and 36-bit data paths - Width expansion to 36-bit per package - Depth expansion to 2048 words per package * 20ns read/write cycle time, 12ns access time * Read and write clocks can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) * Programmable almost-empty and almost-full flags * Empty and Full flags signal FIFO status * Half-Full flag capability in single device configuration * Enable puts output data bus in high impedance state * High-performance submicron CMOS technology * Available in a 121-lead, 16 x 16 mm plastic Ball Grid Array (BGA) * Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications DESCRIPTION: The IDT72805LB/72815LB/72825LB are dual 18-bit-wide synchronous (clocked) first-in, first-out (FIFO) memories. These devices are functionally equivalent to two IDT72205LB/ 72215LB/72225LB FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, local area networks (LANs), and interprocessor communication. Each of the two FIFOs contained in the IDT72805LB/ 72815LB/72825LB has an 18-bit input data port (D0 - D17) and an 18-bit output data port (Q0 - Q17). Each input port is controlled by a free-running Write Clock (WCLK) and a data input Write Enable pin (WEN). Data is written into each array on every rising clock edge of the appropriate Write Clock (WCLK) when its corresponding Write Enable line (WEN) is asserted. FFA FUNCTIONAL BLOCK DIAGRAM WCLKA WENA DA0-DA17 HFA/(WXOA) PAEA EFA WCLKB PAFA LDA WENB DB0-DB17 LDB ** WRITE CONTROL LOGIC WRITE POINTER INPUT REGISTER OFFSET REGISTER ** WRITE CONTROL LOGIC INPUT REGISTER OFFSET REGISTER * * RAM ARRAY 256 x 18 512 x 18 1024 x 18 * * FLAG LOGIC READ POINTER READ CONTROL LOGIC FLA WXIA (HFA)/WXOA WRITE POINTER * * RAM ARRAY 256 x 18 512 x 18 1024 x 18 * * FLAG LOGIC FFB PAFB EFB PAEB HFB/ (WXOB) READ POINTER READ CONTROL LOGIC RXIA RXOA RSA EXPANSION LOGIC OUTPUT REGISTER ** EXPANSION LOGIC OUTPUT REGISTER * * RESET LOGIC RESET LOGIC OEA QA0-QA17 RCLKA RENA WXIB FLB RSB RXOB RXIB (HFB)/WXOB OEB RCLKB QB0-QB17 RENB 3139 drw 01 The IDT logo is a registered trademark, and SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE (c)1996 Integrated Device Technology, Inc For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-839 DECEMBER 1996 DSC-3139/2 5.17 1 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED) The output port of each FIFO bank is controlled by a Read Clock pin (RCLK) and a Read Enable pin (REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clock lines can run asynchronously to one another for dual clock operation. An Output Enable pin (OE) is provided on the read port of each FIFO for three-state output control. Each of the two FIFOs has fixed flags, an Empty (EF) and a Full (FF). Two kinds of programmable flags, an Almost-Empty (PAE) and an Almost-Full (PAF), are provided to improve the utilization of each FIFO memory bank. The offset loading of the programmable flags is controlled by a simple state machine and is initiated by asserting the load pin (LD). A Half-Full flag (HF) is available for each FIFO that is implemented as a single device. The IDT72805LB/72815LB/72825LB are depth expandable using a daisy-chain technique. A set of expansion pins (XI and XO) are provided for each FIFO. In depth expansion configuration, FL is grounded on the first device and set high for all other devices in the daisy-chain. The IDT72805LB/72815LB/72825LB is fabricated using IDT's high speed submicron CMOS technology. PIN CONFIGURATION PIN 1 A WCLKA DA3 DA1 DA0 DB13 DB16 RCLKB LDB OEB DB17 RSB EFB GND QB17 QB16 B PAFA FFA RXOA QA1 DA4 WENA WXIA QA2 DA2 DB12 DB15 RENB GND QB15 QB14 C RXIA QA0 DA5 DB14 DB11 QB13 QB11 D FLA WXOA/ HFA VCC DB8 DB10 DB7 VCC QB12 QB10 QB8 E QA4 QA3 PAEA GND DB9 DB6 VCC VCC QB9 QB7 F QA5 QA6 GND GND GND VCC GND QB6 QB5 G QA7 QA9 VCC VCC DA6 DA9 PAEB DA8 WXOB/ HFB FLB DB5 QB3 QB4 QB1 H QA8 QA10 QA12 VCC DA7 DA10 QB2 QB0 RXOB FFB PAFB WCLKB J QA11 QA13 GND DA17 GND DA11 DA14 WXIB WENB DB1 RXIB DB4 K QA14 QA15 EFA RSA OEA LDA RENA RCKLA DA15 DA12 DB2 L QA16 QA17 DA16 DA13 DB0 DB3 1 2 3 4 5 6 7 8 9 10 11 3139 drw 02 BGA (BG 121-1) TOP VIEW 5.17 2 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Symbol DA0-DA17 DB0-DB17 Name Data Inputs Reset I/O I I Description Data inputs for a 18-bit bus. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full. When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW. RSA RSB WCLKA WCLKB Write Clock Write Enable I I WENA WENB RCLKA RCLKB Read Clock Read Enable I I When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty. When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. RENA RENB OEA OEB LDA LDB FLA FLB WXIA WXIB RXIA RXIB EFA EFB PAEA PAEB PAFA PAFB FFA FFB WXOA/HFA WXOB/HFB RXOA RXOB QA0-QA17 QB0-QB17 VCC GND Output Enable Load I I First Load I In the single device or width expansion configuration, FL is grounded. In the depth expansion configuration, FL is grounded on the first device (first load device) and set to HIGH for all other devices in the daisy chain. In the single device or width expansion configuration, WXI is grounded. In the depth expansion configuration, WXI is connected to WXO (Write Expansion Out) of the previous device. In the single device or width expansion configuration, RXI is grounded. In the depth expansion configuration, RXI is connected to RXO (Read Expansion Out) of the previous device. When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. When LD is LOW, data on the inputs D0-D9 is written to the offset and depth registers on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0-Q9 is read from the offset and depth registers on the LOW-toHIGH transition of the RCLK, when REN is LOW. Write Expansion Input Read Expansion Input Empty Flag Programmable Almost-Empty Flag Programmable Almost-Full Flag Full Flag Write Expansion Out/Half-Full Flag Read Expansion Out Data Outputs Power Ground I I O O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default offset at reset is 31 from empty for 72805LB, 63 from empty for 72815LB, and 127 from empty for 72825LB. O When PAF is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The default offset at reset is 31 from full for 72805LB, 63 from full for 72815LB, and 127 from full for 72825LB. When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the FIFO is written. O O O O In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location in the FIFO is read. Data outputs for a 18-bit bus. 8 Vcc pins 9 GND pins 3139 tbl 01 5.17 3 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TA TBIAS TSTG IOUT Rating Terminal Voltage with respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 50 Unit V C C C mA RECOMMENDED DC OPERATING CONDITIONS Symbol VCC GND VIH VIL(1) NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.0 -- Typ. 5.0 0 -- -- Max. 5.5 0 -- 0.8 Unit V V V V 3139 tbl 03 NOTE: 3139 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maimum rating conditions for extended periods may affect reliabilty. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V 10%, TA = 0C to +70C) IDT72805LB IDT72815LB IDT72825LB Commercial tCLK = 20, 25, 35ns Symbol ILI (1) (2) Parameter Input Leakage Current (any input) Output Leakage Current Output Logic "1" Voltage, IOH = -2 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current Average Standby Current (All Input = VCC - 0.2V, except RCLK and WCLK which are free-running) Min. -1 -10 2.4 -- -- -- Typ. -- -- -- -- -- -- Max 1 10 -- 0.4 250 80 Unit A A V V mA mA ILO VOH VOL ICC1(3) ICC2(3) NOTES: 1. Measurements with 0.4 VIN VCC. 2. OE VIH, 0.4 VOUT VCC. 3. Tested at f = 20MHz with outputs unloaded. Icc limits applicable when using both banks of FIFOs simultaneously. 3139 tbl 04 CAPACITANCE (TA = +25C, f = 1.0MHz) Symbol CIN (2) Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 10 Unit pF pF 3139 tbl 05 COUT(1,2) NOTES: 1. With output deselected, (OE = HIGH). 2. Characterized values, not currently tested. 5.17 4 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V 10%, TA = 0C to +70C) 72805LB20 72815LB20 72825LB20 Min. Max. -- 2 20 8 8 5 1 5 1 20 12 12 -- 0 -- 1 -- -- -- -- -- -- 8 8 14 14 50 12 -- -- -- -- -- -- -- -- -- -- 35 -- 9 9 12 12 30 30 30 12 -- -- -- -- Commercial 72805LB25 72815LB25 72825LB25 Min. Max. -- 3 25 10 10 6 1 6 1 25 15 15 -- 0 -- 1 -- -- -- -- -- -- 10 10 16 16 40 15 -- -- -- -- -- -- -- -- -- -- 40 -- 12 12 15 15 35 35 35 15 -- -- -- -- 72805LB35 72815LB35 72825LB35 Min. Max. -- 3 35 14 14 7 2 7 2 35 20 20 -- 0 -- 1 -- -- -- -- -- -- 14 15 18 18 28.6 20 -- -- -- -- -- -- -- -- -- -- 45 -- 15 15 20 20 40 40 40 20 -- -- -- -- Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE tHF tXO tXI tXIS tSKEW1 tSKEW2 Parameter Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low-Z(2) Output Enable to Output Valid Output Enable to Output in High-Z(2) Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag Clock to Programmable Almost-Empty Flag Clock to Half-Full Flag Clock to Expansion Out Expansion In Pulse Width Expansion In Set-Up Time Skew time between Read Clock & Write Clock for Full Flag Skew time between Read Clock & Write Clock for Empty Flag Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3139 tbl 06 NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested. 5V 1.1K D.U.T. AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1 3139 tbl 07 680 30pF* 3139 drw 05 Figure 1. Output Load * Includes jig and scope capacitances. 5.17 5 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE SIGNAL DESCRIPTIONS: INPUTS: DATA IN (DA0 - DA17, DB0 - DB17) Data inputs for 18-bit wide data. CONTROLS: RESET (RSA RSB RSA, RSB) Reset is accomplished whenever the Reset (RSA, RSB) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. The Full Flag (FFA, FFB), Half-Full Flag (HFA, HFB), and Programmable Almost-Full Flag (PAFA, PAFB) will be reset to HIGH after tRSF. The Empty Flag (EFA, EFB) and Programmable Almost-Empty Flag (PAEA, PAEB) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. WRITE CLOCK (WCLKA, WCLKB) A write cycle is initiated on the LOW-to-HIGH transition of the write clock (WCLKA, WCLKB). Data set-up and hold times must be met with respect to the LOW-to-HIGH transition of WCLK. The write and read clocks can be asynchronous or coincident. WRITE ENABLE (WENA WENB WENA, WENB) When Write Enable (WENA, WENB) is LOW, data can be loaded into the input register and RAM array on the LOW-toHIGH transition of every WCLK. Data is stored in the RAM array sequentially and independently of any on-going read operation. When WEN is HIGH, the input register holds the previous data and no new data is loaded into the FIFO. To prevent data overflow, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the FF will go HIGH after tWFF allowing a write to begin. WEN is ignored when the FIFO is full. READ CLOCK (RCLKA, RCLKB) Data can be read on the outputs on the LOW-to-HIGH transition of the read clock (RCLKA, RCLKB), when the Output Enable (OEA, OEB) is set LOW. The write and read clocks can be asynchronous or coincident. READ ENABLE (RENA RENB RENA, RENB) When Read Enable (RENA, RENB) is LOW, data is loaded into the RAM array to the output register on the LOW-to-HIGH transition of the RCLK. When REN is HIGH, the output register holds the previous data and no new data is loaded into the register. When all the data has been read from the FIFO, EF will go LOW, inhibiting further read operations. Once a write is performed, the EF will go HIGH after tREF and a read can begin. REN is ignored when the FIFO is empty. OUTPUT ENABLE (OEA OEB OEA, OEB) When Output Enable (OEA, OEB) is enabled (LOW), the parallel output buffers receive data from the output register. When OE is disabled (HIGH), the Q output data bus is in a high-impedance state. LOAD (LDA LDB LDA, LDB) The IDT72805LB/72815LB/72825LB devices contain two 10-bit offset registers with data on the inputs, or read on the outputs. When the Load (LDA, LDB) pin is set LOW and WEN is set LOW, data on the inputs D0-D19 is written into the Empty offset register on the first LOW-to-HIGH transition of WCLK. When LD and WEN are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of WCLK. The third transition of WCLK again writes to the Empty offset register. However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing LD HIGH, the FIFO is returned to normal read/ write operation. When LD is set LOW, and WEN is LOW, the next offset register in sequence is written. When LD is LOW and WEN is HIGH, the WCLK input is disabled; then a signal at this input can neither increment the write offset register pointer, nor execute a write. The contents of the offset registers can be read on the output lines when LD is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of RCLK. The act of reading the control registers employs a dedicated read offset register pointer. (The read and write pointers operate independently). A read and a write should not be performed simultaneously to the offset registers. LDA WENA WCLKA(1) LDB WENB WCLKB(1) 0 0 Selection Writing to offset registers: Empty Offset Full Offset 0 1 1 1 0 1 No Operation Write Into FIFO No Operation NOTE: 3139 tbl 08 1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. Figure 2. Write Offset Register 5.17 6 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE FIRST LOAD (FLA FLB FLA, FLB) First Load (FLA, FLB) is grounded to indicate operation in the Single Device or Width Expansion mode. In the Depth Expansion configuration, FL is grounded to indicate it is the first deBvice loaded and is set to HIGH for all other devices in the daisy chain. (See Operating Configurations for further details.) WRITE EXPANSION INPUT (WXIA WXIB WXIA, WXIB) This is a dual purpose pin. Write Expansion In (WXIA, WXIB) is grounded to indicate operation in the Single Device or Width Expansion mode. WXI is connected to Write Expansion Out (WXOA, WXOB) of the previous device in the Depth Expansion or Daisy Chain mode. READ EXPANSION INPUT (RXIA RXIB RXIA, RXIB) This is a dual purpose pin. Read Expansion In (RXIA, RXIB) is grounded to indicate operation in the Single Device or Width Expansion mode. RXI is connected to Read Expansion Out (RXOA, RXOB) of the previous device in the Depth Expansion or Daisy Chain mode. OUTPUTS: FULL FLAG (FFA FFB FFA, FFB) The Full Flag (FFA, FFB) will go LOW, inhibiting further write operation, indicating that the device is full. If no reads are performed after RS, FF will go LOW after 256 writes for the IDT72805LB, 512 writes for the IDT72815LB, 1024 writes for the IDT72825LB. FF is updated on the LOW-to-HIGH transition of WCLK. EMPTY FLAG (EFA EFB EFA, EFB) The Empty Flag (EFA, EFB) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating the device is empty. The EF is updated on the LOW-to-HIGH transition of RCLK. 17 9 EMPTY OFFSET REGISTER DEFAULT VALUE 001FH (72805) 003FH (72815): 007FH (72825) 0 17 9 FULL OFFSET REGISTER DEFAULT VALUE 001FH (72805) 003FH (72815): 007FH (72825) 0 3139 drw 03 NOTE: 1. Any bits of the offset register not being programmed should be set to zero. Figure 3. Offset Register Location and Default Values TABLE I -- STATUS FLAGS Number of Words in FIFO 72805 0 1 to n(1) (n + 1) to 128 129 to (256-(m+1)) (256-m)(2) 256 to 255 72815 0 1 to n(1) (n + 1) to 256 257 to (512-(m+1)) (512-m)(2) 512 to 511 72825 0 1 to n(1) (n + 1) to 512 513 to (1024-(m+1)) (1024-m)(2) to 1023 1024 FFA FFB H H H H H L PAFA PAFB H H H H L L HFA HFB H H H L L L PAEA PAEB L L H H H H EFA EFB L H H H H H 3139 tbl 09 NOTES: 1. n = Empty Offset (Default Values : 72805 n=31, 72815 n = 63, 72825 n = 127) 2. m = Full Offset (Default Values : 72805 n=31, 72815 n = 63, 722825 n = 127) PROGRAMMABLE ALMOST-FULL FLAG (PAFA PAFB PAFA, PAFB) The Programmable Almost-Full Flag (PAFA, PAFB) will go LOW when FIFO reaches the Almost-Full condition. If no reads are performed after RS, the PAF will go LOW after (256m) writes for the IDT72805LB, (512-m) writes for the IDT72815LB, (1024-m) writes for the IDT72825LB. The offset "m" is defined in the FULL offset register. If there is no Full offset specified, the PAF will be LOW when the device is 31 away from completely full for 72805LB, 63 away from completely full for 72815LB, and 127 away from completely full for 72825LB. The PAF is asserted LOW on the LOW-to-HIGH transition of the WCLK. PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Thus PAF is asychronous. 5.17 7 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE PROGRAMMABLE ALMOST-EMPTY FLAG (PAEA PAEA, The Programmable Almost-Empty Flag (PAEA, PAEB) will go LOW when the read pointer is "n" locations less than the write pointer. The offset "n" is defined in the EMPTY offset register. If there is no Empty offset specified, PAE will be LOW when the device is 31 away from completely empty for 72805LB, 63 away from completely empty for 72815LB, and 127 away from completely empty for 72825LB. The PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. Thus PAF is asychronous. WRITE EXPANSION OUT/HALF-FULL FLAG (WXOA HFA, WXOB HFB) WXOA/HFA WXOB/HFB This is a dual-purpose output. In the Single Device and Width Expansion mode, when WXI is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full Flag goes LOW PAEB PAEB) and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HFA, HFB) is then reset to HIGH by the LOW-to-HIGH transition of the read clock (RCLK). The HF is asychronous. In the Depth Expansion or Daisy Chain mode, WXI is connected to WXO of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device writes to the last location of memory. READ EXPANSION OUT (RXOA, RXOB RXOA, RXOB) In the Depth Expansion or Daisy Chain configuration, Read Expansion In (RXIA, RXIB) is connected to Read Expansion Out (RXOA, RXOB) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device reads from the last location of memory. DATA OUTPUTS (Q0A-QA17, QB0-QB17) Q0-Q17 are data outputs for 18-bit wide data. t RS RS tRSS t RSR REN, WEN, LD t RSF EF , PAE t RSF FF, PAF, HF t RSF OE = 1(1) Q0 - Q17 OE = 0 NOTES: 1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 2. The clocks (RCLK, WCLK) can be free-running during reset. Figure 4. Reset Timing(2) 3139 drw 04 5.17 8 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE t CLK t CLKH WCLK t DS D0 - D17 DATA IN VALID t ENS t DH t CLKL t ENH NO OPERATION WEN t WFF t WFF FF t SKEW1 (1) RCLK REN 3139 drw 05 NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 5. Write Cycle Timing 5.17 9 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE t CLK t CLKH RCLK t ENS t ENH NO OPERATION t CLKL REN t REF t REF EF tA Q0 - Q17 t OLZ VALID DATA t OHZ t OE OE t SKEW2 WCLK (1) WEN 3139 drw 06 NOTE: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle Timing 5.17 10 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE WCLK t D0 - D17 t ENS DS D0 (first valid write) D1 D2 D3 D4 WEN t FRL(1) tSKEW2 RCLK EF REN t REF tA Q0 - Q17 D0 t OLZ t OE tA D1 OE 3139 drw 07 NOTES: 1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 2. The first word is available the cycle after EF goes HIGH, always. Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write 5.17 11 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 NO WRITE COMMERCIAL TEMPERATURE RANGE NO WRITE WCLK tSKEW1 D0 - D17 t WFF (1) tDS DATA WRITE t WFF t SKEW1 (1) t DS DATA WRITE FF WEN RCLK t ENS tENH tWFF t ENH tENS REN OE Q0 - Q17 LOW tA DATA IN OUTPUT REGISTER DATA READ tA NEXT DATA READ 3139 drw 11 NOTE: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. Figure 8. Full Flag Timing 5.17 12 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE WCLK tDS tDS D0 - D17 tENS DATA WRITE 1 tENH tENS DATA WRITE 2 tENH WEN tFRL tSKEW2 RCLK (1) tFRL tSKEW2 (1) tREF tREF EF REN OE LOW tA Q0 - Q17 DATA IN OUTPUT REGISTER DATA READ 3139 drw 09 NOTE: 1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW2. or tCLK + tSKEW2. The Latency Timing apply only at the Empty Boundary (EF = LOW). Figure 9. Empty Flag Timing 5.17 13 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH WCLK tENS tENH tCLKL LD tENS WEN tDS D0-D15 PAE OFFSET PAF OFFSET D0-D11 3139 drw 10 tDH PAE OFFSET Figure 10. Write Programmable Registers tCLK tCLKH RCLK tENS tENH tCLKL LD tENS REN tA Q0-Q15 UNKNOWN PAE OFFSET PAF OFFSET 3139 drw 11 PAE OFFSET Figure 11. Read Programmable Registers 5.17 14 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE tCLKH WCLK tENS tCLKL tENH WEN tPAE n + 1 words in FIFO tPAE RCLK tENS n words in FIFO PAE REN 3139 drw 12 NOTE: 1. PAE is offset = n. Number of data words written into FIFO already = n. Figure 12. Programmable Almost Empty Flag Timing tCLKH WCLK (1) tENS tCLKL tENH WEN tPAF PAF Full - m words in FIFO(2) tPAF Full - (m + 1) words in FIFO(3) RCLK tENS REN 3139 drw 13 NOTES: 1. PAF offset = m. Number of data words written into FIFO already = 256 - (m + 1) for the IDT72805LB, 512 - (m + 1) for the IDT72815LB, 1024 - (m + 1) for the IDT72825LB. 2. 256 - m words in IDT72805LB, 512 - m words in IDT72815LB, 1024 - m words in IDT72825LB. 3. 256 - (m + 1) words in IDT72805LB, 512 - (m + 1) words in IDT72815LB, 1024 - (m + 1) words in IDT72825LB. Figure 13. Programmable Almost-Full Flag Timing 5.17 15 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE tCLKH WCLK tENS tCLKL tENH WEN tHF HF Half Full or Less Half Full + 1 or More tHF Half Full or Less RCLK tENS REN 3139 drw 14 Figure 14. Half-Full Flag Timing t CLKH WCLK Note 1 t XO t XO WXO t ENS 3139 drw 15 WEN NOTE: 1. Write to Last Physical Location. Figure 15. Write Expansion Out Timing t CLKH RCLK Note 1 t XO t XO RXO t ENS 3139 drw 16 REN NOTE: 1. Read from Last Physical Location. Figure 16. Read Expansion Out Timing 5.17 16 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE t XI WXI t XIS WCLK 3139 drw 17 Figure 17. Write Expansion In Timing t XI RXI t RCLK XIS 3139 drw 18 Figure 18. Read Expansion In Timing OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION Each of the two FIFOs contained in a single IDT72805LB/ 72815LB/72825LB may be operated as a stand-alone device when the application requirements are for 256/512/1024 words or less. The IDT72805LB/72815LB/72825LB are in a single Device Configuration when the Write Exansion In (WXI), Read Expansion In (RXI), and First Load (FL) control inputs are grounded (Figure 19). RESET (RS) WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD (LD) DATA IN (D0 - D17) FULL FLAG (FF) PROGRAMMABLE (PAE) HALF-FULL FLAG (HF) IDT 72805LB/ 72815LB/ 72825LB FIFO A or B EMPTY FLAG (EF) PROGRAMMABLE (PAF) READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) DATA OUT (Q0 - Q17) READ EXPANSION IN (RXI) FIRST LOAD (FL) WRITE EXPANSION IN (WXI) 3139 drw 19 Figure 19. Block Diagram of Single 256 x 18/512 x 18/1024 x 18 Synchronous FIFO (One of the Two FIFOs contained in the 72805/72815/72825) 5.17 17 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE WIDTH EXPANSION CONFIGURATION -- Word width may be increased simply by connecting together the control signals of FIFOs A and B. A composite flag should be created for each of the end-point status flags (EFA and EFB, also FFA and FFB). The partial status flags (PAEA and PAEB, also 18 PAFA and PAFB) can be detected from any one device. Figure 20 demonstrates a 36-bit word width using the two FIFOs contained in one IDT72805/72815/72825. Any word width can be attained by adding additional IDT2805/72815/ 72825. * 72805/ 72815/ 72825 DATA IN WRITE CLOCK WRITE ENABLE 36 RESET RSA DB0 - DB17 RSB FIFO B * * 18 DA0 - DA17 WCLKA FIFO A EFA EFB RCLKB EMPTY FLAG READ CLOCK READ ENABLE OUTPUT ENABLE RCLKA WCLKB WENA FFA FFB 256x18 512x18 1024x18 RENA WENB OEA 256x18 512x18 1024x18 RENB OEB QB0 - QB17 18 FULL FLAG * * 36 DATA OUT QA0-QA17 18 3139 drw 20 NOTE: 1. Do not tie any output control signals directly together. 2. Tie FLA, FLB, WXIA, WXIB, RXIA and RXIB to GND. Figure 20. Block Diagram of the two FIFOs contained in one 72805/72815/72825 configured for a 36-bit Width Expansion DEPTH EXPANSION CONFIGURATION (WITH PROGRAMMABLE FLAGS) The IDT72805LB/72815LB/72825LB can easily be adapted to applications requiring more than 256/512/1024 words of buffering. Figure 21 shows a Depth Expansion using the two FIFOs contained in one IDT72805LB/72815LB/72825LB. Maximum depth is limited only by signal loading. Follow these steps: 1. The first FIFO must be designated by grounding the First Load (FL) control input. 2. All other FIFOs must have FL in the HIGH state. 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next FIFO. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next FIFO. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together every respective flags for monitoring. The composite PAE and PAF flags are not precise. 5.17 18 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18-BIT, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE WXOA RXOA LDA RCLKA WCLKA RENA OEA WENA RSA DAn Vcc FIRST LOAD QAn FIFO A 1024x18 FLA FFA EFA RXIA DATA OUT DATA IN WXIA WXOB 72825 WRITE CLOCK WRITE ENABLE RESET LOAD RXOB * READ CLOCK READ ENABLE OUTPUT ENABLE * WCLKB RCLKB WENB RSB DBn RENB OEB QBn * LDB FFB FIRST LOAD FIFO B FULL FLAG 1024x18 EFB EMPTY FLAG FLB WXIB RXIB 3139 drw 21 Figure 21. Block Diagram of 2048 x 18 Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration 5.17 19 IDT72805/72815/72825 CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, and 1024 x 18 COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type X Power XX Speed X Package X Process / Temperature Range BLANK Commercial (0C to +70C) BG Ball Grid Array 20 25 35 Commercial Only Clock Cycle Time (tCLK) Speed in Nanoseconds LB Low Power 72805 72815 72825 256 x 18 Dual Synchronous FIFO 512 x 18 Dual Synchronous FIFO 1024 x 18 Dual Synchronous FIFO 3139 drw 22 5.17 20 |
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